8 To 1 Multiplexer Vhdl
In the previous tutorial VHDL tutorial, we designed an 8-bit parity generator and 8-bit parity checker circuits using VHDL.
(If you are not following this VHDL tutorial series one by one, you are requested to go through all previous tutorials of these series before going ahead in this tutorial)
In this tutorial,
ENTITY multiplexertest IS END multiplexertest; ARCHITECTURE behavior OF multiplexertest IS And also you need to change the top entity to multiplexertest instead of testbench. Or if you just rename the testbench module from multiplexer to testbench then you don't need to do the second step. How to make 8x1 Multiplexer using 2 4x1 Multiplexer? As we know a multiplexer has 1 output and 2 n where n is the no. Of select lines. Following is the logic Diagrams for 8x1 Mux using two 4x1 Mux.
- We shall write a VHDL program to build 3×8 decoder and 8×3 encoder circuits
- Verify the output waveform of the program (digital circuit) with the truth table of these encoder and decoder circuits
3×8 Decoder circuit
Truth Table
Now we shall write a VHDL program, compile it, simulate it, and get the output in a waveform. Finely, we shall verify those output waveforms with the given truth table.
(Please go through step by step procedure given in VHDL-tutorial 3 to create a project, edit and compile the program, create a waveform file, simulate the program, and generate output waveforms.)
In previous tutorials, we had used either a data-flow modeling style or structural modeling style. But this time, we shall use a 3rd style that is the behavioral modeling style. Behavioral modeling style is useful in representing sequential digital circuits. The decoder is not a sequential digital circuit, but it will be easier to build this circuit using behavioral style.
VHDL Program
(To know more and get more details about VHDL program(s), please go through the first two tutorials, VHDL tutorial 1 and VHDL tutorial 2 of these series.)
Next, compile the above program – create a waveform file with all inputs and outputs listed – apply different input combinations – save the waveform file, and finally, simulate the project. You will get the following result.
Simulation Waveform
One can easily verify D0-D7 output, that is, at a time, only one output is high, and all others are low as per given input A0-A1-A2 combinations from “000” to “111”.
/free-spyhunter-5-serial-key.html. Now let us build an 8×3 encoder circuit
8×3 encoder circuit
Truth Table
VHDL program Simulation waveforms
As shown in the figure, the input-output waveforms look similar to the decoder because the encoder is just the reverse of the decoder. The input becomes output and vice versa. Here in the given figure, one case is highlighted when D7 input is ‘1’ all outputs a = 1, b=1, and c=1. You can verify other combinations from the truth table.
In the next tutorial, we shall design 8×1 multiplexer and 1×8 de-multiplexer circuits using VHDL.
64 x 1 MULTIPLEXER:-
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity mux_64_1 is
Port ( I : in STD_LOGIC_VECTOR (0 to 63);
s : in STD_LOGIC_VECTOR (5 downto 0);
Y : out STD_LOGIC);
end mux_64_1;
architecture Behavioral of mux_64_1 is
component muxs is
Port ( I : in STD_LOGIC_VECTOR (0 to 7);
s : in STD_LOGIC_VECTOR (2 downto 0);
Y : out STD_LOGIC);
end component;
signal x:std_logic_vector(0 to 7);
begin
u1:muxs port map(I(0 to 7),S(2 downto 0),x(0));
u2:muxs port map(I(8 to 15),S(2 downto 0),x(1));
u3:muxs port map(I(16 to 23),S(2 downto 0),x(2));
u4:muxs port map(I(24 to 31),S(2 downto 0),x(3));
u5:muxs port map(I(32 to 39),S(2 downto 0),x(4));
u6:muxs port map(I(40 to 47),S(2 downto 0),x(5));
u7:muxs port map(I(48 to 55),S(2 downto 0),x(6));
u8:muxs port map(I(56 to 63),S(2 downto 0),x(7));
u9:muxs port map(x,s(5 downto 3),Y);
end Behavioral;
Mux, Subprogram:-
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity muxs is
Port ( I : in STD_LOGIC_VECTOR (0 to 7);
s : in STD_LOGIC_VECTOR (2 downto 0);
Y : out STD_LOGIC);
end muxs;
architecture Dataflow of muxs is
begin
with s select
Y<= I(0) when '000',
I(1) when '001',
I(2) when '010',
I(3) when '011',
I(4) when '100',
I(5) when '101',
I(6) when '110',
I(7) when others;
end Dataflow;
OUT PUT:-
Test bench:-
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
use ieee.std_logic_arith.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY tbmx IS
END tbmx;
ARCHITECTURE behavior OF tbmx IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT mux_64_1
PORT(
I : IN std_logic_vector(0 to 63);
s : IN std_logic_vector(5 downto 0);
Y : OUT std_logic
);
END COMPONENT;
--Inputs
signal I : std_logic_vector(0 to 63) := (others => '0');
signal s : std_logic_vector(5 downto 0) := (others => '0');
--Outputs
signal Y : std_logic;
-- No clocks detected in port list. Replace <clock> below with
-- appropriate port name
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: mux_64_1 PORT MAP (
I => I,
s => s,
Y => Y
);
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
I<= conv_std_logic_vector(2751055,64);
for i in 0 to 63 loop
s<= conv_std_logic_vector(i,6);
wait for 100 ns;
end loop;
-- insert stimulus here
wait;
end process;
END;